The ZipCPU by Gisselquist Technology

The ZipCPU blog, featuring how to discussions of FPGA and soft-core CPU design. This site will be focused on Verilog solutions, using exclusively OpenSource IP products for FPGA design. Particular focus areas include topics often left out of more mainstream FPGA design courses such as how to debug an FPGA design.

Blog Posts

ZipCPU Lesson: If it's not tested, it doesn't work.
A Coming Economic Downturn? or Worse?
Quiz #20: Using $stable in a multiclock environment
Learning AXI: Where to start?
Bringing up a new piece of hardware -- what can go wrong?
Rethinking Video with AXI video streams
AXI Stream is broken
2020 and 2021 in review
Quiz #19: Using disable iff in a concurrent assertion
Creating a Simple AXI-Lite Master for the Hexbus
Envisioning the Ultimate I2C Controller
Clock Gating
Upgrading the ZipCPU's memory unit from AXI4-lite to AXI4
Quiz #18: Failures in clocked immediate assertions
AXI Handshaking Rules
Measuring AXI latency and throughput performance
Quiz #17: Induction failures
The other half of the Gospel
CPU based simulation, first thoughts
Quiz #16: Immediate assertions in the presence of asynchronous resets
Building a Better Verilog Multiply for the ZipCPU
Examples of AXI4 bus masters
Quiz #15: Pass-through memory
Fixing Xilinx's Broken AXI-lite Design in VHDL
Building a Simple AXI-lite Memory Controller
Common AXI Themes on Xilinx's Forum
Whatever happened to the ZipOS?
Lessons learned while building an ASIC design
The FPGA designer who didn't get the job
Ultimate Logic
Quiz #14: Two nearly identical frequencies
Formally verifying register handling
Is it possible to make a living as a solo digital design engineer?
Spectrograms need Window Functions
A fun Friday evening--verifying an AXI-lite slave
Moving values and strobes cross clock domains
Quiz #13: Temporal assertion equivalences
Run length encoding an AXI stream
Driving an output on both edges of the clock
Building a Downsampling Filter
I have a brand new piece of IP. How shall I verify it?
Measuring clock speed
The hard part of building a bursting AXI Master
Four keys to getting your design to work the first time
Quiz #12: Catching extraneous acknowledgments
Building a Protocol Firewall
Debugging AXI Streams
Adding an AXI-Lite interface to your Verilator test script
Re: What does your design flow look like?
Building a basic AXI Master
Cheap Spectral Estimation
Locally resetting an AXI component
Adjusting our logic PLL to handle I&Q
Buidilng an AXI-Lite slave the easy way
The Faith of a Mustard Seed
A Histogram Gone Bad
Quiz #11: Induction and clock enables
Quiz #10: Checking stall conditions
Lessons in Hardware Reuse
2019: AXI Meets Formal Verification
The Christmas Gospel
Using a Histogram to Debug A/D Data Streams
Quiz #9: Immediate assertions midst blocking assignments
Quiz #8: Will this pass a bounded model check?
The ZipCPU meets blinky
Formally Verifying a General Purpose Ultra-Micro Controller
Quiz #7: Returning to $past() and our counter again
Putting the pieces together to build a data recorder
Is formal verfication enough, or is simulation required?
Quiz #6: Synchronous logic in Asynchronous contexts
AXI Verification, the story so far
Understanding AutoFPGA's address assignment algorithm
Quiz #5: Immediate vs Concurrent Assertions
Connecting lots of slaves to a bus without using a lot of logic
Quiz #4: If this counter is never triggered, can we prove it'll never leave zero?
Technology Debt and AutoFPGA, the bill just came due
Xilinx deleted this post
Quiz #3: Will formal verification prove this counter keeps its bounds?
Planning an Intermediate Design Tutorial
Quiz #2: Will this counter pass formal verification?
Quiz #1: Will the assertion below ever fail?
Just how long does a formal proof take to finish?
Lessons learned while building crossbar interconnects
Breaking all the rules to create an arbitrary clock signal
Building the perfect AXI4 slave
Building a Skid Buffer for AXI processing
Examining Xilinx's AXI demonstration core
Understanding AXI Addressing
Project Ideas: PMod AMP2
Applying Formal Methods to the Events of the Resurrection
The most common AXI mistake
The ZipCPU's Interrupt Controller
Logic usage and decoding return results with cascaded multiplexers
Building a universal QSPI flash controller
Introducing the ArrowZip ZipCPU design, featuring the Max-1000
Using Sequence Properties to Verify a Serial Port Transmitter
Why does blinky make a CPU appear to be so slow?
Debugging a CPU
Building a custom yet functional AXI-lite slave
ZipCPU highlights from 2018
Using a formal property file to verify an AXI-lite peripheral
AutoFPGA's linker script support gets an update
Makefiles for formal proofs with SymbiYosys
Swapping assumptions and assertions doesn't work
Building a video controller: it's just a pair of counters
Accessing the registers of a SoC+FPGA
Taking a look at the TinyFPGA BX
To my new readers and my new twitter followers, welcome!
An Open Source Pipelined FFT Generator
It's time for ORCONF 2018!
My design works in simulation, but not in hardware. Can formal methods help me?
Handling multiple clocks with Verilator
RE: Building a simulation for my design? What does that mean?
How to build a SPI Flash Controller for an FPGA
Reasons why Synthesis might not match Simulation
Why I like Formal: the ZipCPU and the ICO board
What does Formal Development look like in Practice?
Formally Verifying Memory and Cache Components
Crossing clock domains with an Asynchronous FIFO
Formally Verifying Asynchronous Components
A Slow but Symmetric FIR Filter Implementation
Updated Projects List
Aggregating verified modules together
ZipTimer: A simple countdown timer
Formally Verifying an Asynchronous Reset
What would you like to see on the ZipCPU blog?
Will formal methods ever find a bug in a working CPU?
Resurrection Day!
Quadratic fits are entirely inappropriate for DSP
Pipelining a Prefetch
Is formal really all that hard?
An Exercise in using Formal Induction
Want to use ZBasic? Let's have some fun--no actual FPGA required!
Debugging a Cyclone-V
ZipCPU toolchain and initial test
Updating ZipCPU files
Interpolation is just a special type of convolution
A Quick Introduction to the ZipCPU Instruction Set
Top 10 ZipCPU blog posts for 2017
A better filter implementation for slower signals
Mystery post: The ugliest bug I've ever encountered
Arrow's Max-1000: A gem for all the wrong reasons
Building a Simple Logic PLL
Building a Numerically Controlled Oscillator
Testing the fast, generic FIR filter
Thank you!
Measuring the frequency response of a filter under test
Building a prefetch module for the ZipCPU
Generating more than one bit at a time with an LFSR
An example LFSR
A Configurable Signal Delay Element
Building Formal Assumptions to Describe Wishbone Behaviour
The Interface to a Generic Filtering Testbench
Good Software Engineering Principles Apply to Students Too
Generating Pseudo-Random Numbers on an FPGA
Some Simple Clock-Domain Crossing Solutions
My first experience with Formal Methods
Just some notes to new readers of the ZipCPU blog
Implementing the Moving Average (Boxcar) filter
FPGAs vs ASICs
It's all about the interfaces
Using AutoFPGA to connect simple registers to a debugging bus
A Brief Introduction to AutoFPGA
A CORDIC testbench
A Cheaper Fast FIR Filter
Understanding the effects of Quantization
Clocks for Software Engineers
Demonstrating the improved PWM waveform
Building a high speed Finite Impulse Response (FIR) Digital Filter
Even I get stuck in FPGA Hell
Glad I went to ORCONF
Off to ORCONF-2017!
Reinventing PWM
Big Money Engineering Integrity
CORDIC part two: rectangular to polar conversion
Using a CORDIC to calculate sines and cosines in an FPGA
Building a quarter sine-wave lookup table
Debugging your soft-core CPU within an FPGA
The ZipCPU's pipeline logic
Rules for new FPGA designers
Two of the Simplest Digital filters
Strategies for pipelining logic
What would cause you to lie?
A Simple ALU, drawn from the ZipCPU
Series: Debouncing in Digital Logic
Using a debug-bus to Measure Bouncing
Measuring Contact Bounce
How to eliminate button bounces with digital logic
Visualizing Contact Bounce
ZipCPU Advertising
Writing your own VCD File
Linear Interpolation
Getting the basic FIFO right
Windows FPGA designers may not need a Linux machine ... yet
How to build a simulation based debugger for your own soft-core CPU
How to Debug a DSP algorithm
Rounding Numbers without Adding a Bias
Bit growth in FPGA arithmetic
A Basic Upsampling Linear Interpolator
Verilator doesn't find everything (today)
Design Needs when Debugging a SoftCore CPU
The simplest sine wave generator within an FPGA
Getting Started with the Wishbone Scope
Finishing off the debugging bus: building a software interface
Why you want a debug port into your FPGA
Simulating an FPGA through the debugging interface
My own FPGA debugging philosophy
Building a very simple wishbone interconnect
Taking a New Look at Verilator
Putting our Debugging Bus RTL Components Together
Sending bus idle notifications down the line
Why Use a Network Interface to your FPGA
Support me on Patreon
The debugging bus: a goal for FPGA interaction
Adding interrupt reporting to our debugging bus
How to send our bus results back out the serial port
No PI for you
How to create bus command words, from a 7-bit data stream
Minimizing FPGA Resource Utilization
A College Student's Response to the FPGA Design Process
Building a Simple Wishbone Master
Building A Simple In-Circuit Logic Analyzer
Nearest Neighbor Interpolation
An Overview of a Wishbone-UART Bridge
Campus Sidewalks and FPGA Design
Controlling Timing within an FPGA
The Actual FPGA Design Process
Building a simple wishbone slave
Bus Select Lines
FFT debugging
Debugging an FPGA through the serial port--first steps
That first serial port: Debugging when you are blind
Building a simple bus
Moving to memory
A Vision for Controlling FPGA Logic
Which comes first: the CPU or the peripherals?
Knight Rider
FPGA Hell
Blinky
Most common Digilent FPGA support requests
Cannot be done
Welcome to the ZipCPU blog!
The ZipCPU by Gisselquist Technology

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